Ferroelectric field-effect transistors (Fe-FETs) have emerged as a key technology for next generation logic computing and non-volatile memory (NVM), offering low-power consumption and multifunctional characteristics. Notably, hafnium zirconium oxide (HZO), a novel fluorite-structured ferroelectric material, demonstrates exceptional scalability, high compatibility with complementary metal oxide-semiconductor (CMOS) processes, and outstanding material stability. Notably, ultrathin HZO layers (3–5 nm) are well suited for Fe-FET logic devices, whereas thicker HZO films (10–12 nm) are optimal for Fe-FET-based NVM applications. This article systematically reviews recent advances in HZO-based Fe-FETs, covering negative capacitance field-effect transistors (FETs), super-high-k FETs, and Fe-FET NVM applications, while also addressing current challenges. This comprehensive analysis provides technical insights for advancing HZO-based Fe-FET technology.

Professor Yung-Chun Wu earned his B.S. degree in Physics from National Central University in 1996, followed by an M.S. degree in Physics from National Taiwan University in 1998, and a Ph.D. degree from the Institute of Electronics at National Chiao Tung University in 2005. From 1998 to 2002, he worked as an assistant researcher at the Taiwan Semiconductor Research Institute in Hsinchu, Taiwan, focusing on the advancement of nanoelectronics device technology and electron beam lithography techniques. He joined the Department of Engineering and System Science at National Tsing Hua University in Hsinchu, Taiwan, in 2006, where he currently serves as a full professor and holds an adjunct professorship at the College of Semiconductor Research. As an IEEE Senior Member, his research expertise spans semiconductor device fabrication and integration, semiconductor device physics and TCAD simulation, as well as memory process and integration.

Professor Wu has published more than 100 peer-reviewed articles in SCI-indexed journals on semiconductor device technology, with the majority appearing in IEEE publications, and holds several U.S. patents. His scholarly contributions include authoring the English textbook Book：Semiconductor Processes and Integration. Publisher: Cengage; 1st ed. 2026 edition, Softcover: 496 pages ISBN 978-6267533420. TCAD Simulation for CMOS Nanoelectronic Devices" (Springer, 2017, ISBN: 9789811030659) and the Chinese textbook "Semiconductor Processes and Integration" (Tsang Hai Book Publishing Co., August 2023, ISBN: 9786269729166).

(TBD)

Associate Professor Tzu-Hsuan Chang’s major research areas cover flexible electronics, heterogeneous electronics, and novel nanofabrication techniques. In flexible electronics, he focuses on exploiting flexible thin-film nanomembranes in high-speed, high-power, optoelectronic, and medical applications. The uniqueness of releasable single-crystal nanomembranes can also enable heterogeneous integration of different materials to boost electronic performance beyond what is achievable through traditional epitaxial growth approaches. In nanoelectronics, he focuses on the interactions between small-molecule chemicals and semiconductor materials to enable sub-10-nm fabrication processes.

As CMOS technology enters the Angstrom era, continued transistor scaling is increasingly constrained by electrostatic control, contact resistance, gate dielectric scaling, and process integration. Two-dimensional (2D) semiconductors have emerged as one of the most promising channel materials for extending CMOS technology beyond conventional silicon. This talk will provide an overview of the status and prospects of 2D CMOS technologies, highlighting the key scientific and technological challenges toward practical implementation. Emphasis will be placed on aggressive contacted gate pitch (CGP) scaling, sub-1 nm equivalent oxide thickness (EOT), complementary transistor technologies, contact engineering, and CMOS-compatible process integration. Recent advances in these areas will be reviewed to illustrate the ongoing efforts toward practical 2D CMOS, followed by perspectives on the key technological directions required to realize manufacturable, high-performance, and energy-efficient logic technologies in the post-silicon era.

Tsung-En Lee received the B.S. degree in Electronics Engineering from National Chiao Tung University, Taiwan, in 2014, and the M.S. and Ph.D. degrees in Electrical Engineering and Information Systems from the University of Tokyo, Japan, in 2018 and 2021, respectively. From 2021 to 2024, he was a Principal Engineer at Corporate Research, Taiwan Semiconductor Manufacturing Company (TSMC), where he developed emerging devices and technologies for future CMOS scaling. Since August 2024, he has been an Assistant Professor with the Department of Microelectronics, National Yang Ming Chiao Tung University (NYCU), Taiwan. He is the recipient of the TSMC Junior Fellow, MOE Yushan Young Fellow, NSTC SEED Young Scholar, and NSTC 2030 Emerging Young Scholar fellowships. He has authored and co-authored more than 60 technical publications, including six papers at the IEEE International Electron Devices Meeting (IEDM), four papers at the IEEE/JSAP Symposium on VLSI Technology and Circuits, three Nature-series publications, and four U.S. patents. His research has been recognized with the IEEE IEDM Highlighted Paper Award (2022), the JSAP Young Scientist Award (2020), and the TSMC CR Patent Award (2023). His current research interests span novel-material electronic devices, heterogeneous integration, and design-technology co-optimization (DTCO), including 2D materials, oxide semiconductors, ferroelectric devices, BEOL-compatible devices and memories, and cryogenic CMOS, for future energy-efficient computing.

Research in vertical scaling heterojunction material layers and lateral scaling device emitter size in InP based HBTs have led to THz device operation toward the Tbps data link needs for AI and IoT. Different than Si transistor, III-V transistor base e-h recombination process can provide electrical and optical signal outputs realized in 2003. By incorporated quantum-wells in the transistor base with optical cavity, the transistor laser was first discovered and demonstrated in 2004. OEIC Optical logics can be realized for all optic computing.

Milton Feng is Professor Emeritus of Electrical and Computer Engineering at the University of Illinois Urbana-Champaign. He is known for pioneering research on high-speed III-V heterojunction bipolar transistors, including terahertz transistor operation, and for co-inventing the transistor laser with Nick Holonyak Jr. He is a Fellow of IEEE and OSA and holds 40 U.S. patents.

Heterojunction bipolar transistor structures with unipolar quantum transition structures embedded within the base-collector junction have been modeled, fabricated, and characterized. Inspired by both the Transistor Laser (TL) and Quantum Cascade Laser (QCL), these devices show promise for enabling modulation of coherent light from Mid-Wave Infrared (MWIR) wavelengths through THz frequencies. This talk will review progress on these devices, remaining challenges, and opportunities. Novel electrical and optical performance will also be discussed, including electrical bistability, negative differential resistance, and data on Short-Wave Infrared (SWIR) band-to-band lasing under defined bias conditions. The bias-determined dual-band SWIR and MWIR emission provides a unique capability not possible with other MWIR emitters.

John Dallesasse is the Gregory E. Stillman Professor in Electrical and Computer Engineering in the Grainger College of Engineering at the University of Illinois at Urbana-Champaign (UIUC), where he’s been since 2012. He also has over 20 years of industry experience in technology development and executive management. His technical contributions include, with Nick Holonyak, Jr., the discovery of III‑V Oxidation, which has become an enabling process technology for the fabrication of Vertical-Cavity Surface-Emitting Lasers (VCSELs). He is an IEEE and Optica Fellow, and currently serves as the Editor-in-Chief for the IEEE Journal of Quantum Electronics and as the President-Elect for the IEEE Electron Devices Society.

Silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) with high breakdown voltage, low conduction loss, and fast switching capability, are attractive candidates for high-frequency and high-power applications. However, parasitic capacitances, including gate-to-source (Cgs), gate-to-drain (Cgd), and drain-to-source (Cds) capacitances, significantly affect their electrical performance of switching speed, gate-drive requirements, power loss, and voltage overshoot. In particular, the nonlinear Cgd strongly affects the Miller plateau and switching transition, while Cds contributes to energy loss during hard switching. As operating voltage and switching frequency increase, these parasitic effects become increasingly important. Accurate characterization and modeling of parasitic capacitances are essential for reliable device and circuit design. Therefore, this study investigates the influence of SiC MOSFET parasitic capacitances on electrical characteristics, providing useful guidelines for epitaxial layer and MOSFET structures.

Dr. Kung-Yen Lee received the Ph.D. degrees in electrical and computer engineering from Purdue University, West Lafayette, IN, USA. He is currently a professor with the Department of Engineering Science and Ocean Engineering and Graduate School of Advanced Technology in National Taiwan University. He is the director of NTU-ITRI (National Taiwan University-Industrial Technology Research Institute) Nano Center as well. Prof. Lee has worked on SiC power semiconductor devices, interface between oxide and SiC surface, and fabrication processes over twenty years. In addition, he has served as general chair, technical program committee members and session chairs for international conferences on power devices and power electronics, such as International Conference on Silicon Carbide and Related Materials (ICSCRM), IEEE International Symposium on Power Semiconductor Devices and ICs (ISPSD), IEEE Workshop on Wide Bandgap Power Devices and Applications in Asia (WiPDA-Asia), International Conference on Solid State Devices and Materials (SSDM) and International Future Energy Electronics Conference (IFEEC), etc. He also serves as an Associate Editor of IEEE Transactions on Electron Devices.

I will deliver a presentation reporting our recent progress on CMOS-MEMS based capacitive micromachined ultrasonic transducers (i.e., CMUT on CMOS), including design, modeling, simulation, fabrication, testing, and potential applications. This talk begins with a fabrication platform using CMOS 0.18m technology node and post-CMOS process with a special focus on realizing tiny gaps and high electromechanical coupling resonant transducers to serve as a fundamental building block for ultrasound actuation and sensing. Through this platform, capacitive resonant transducers with multiple-gap configurations can be implemented either horizontally or vertically on the same chip to meet various demands raised by applications; for example, CMUT transmitter (TX) favors large gap spacing to enhance its driving efficiency while receiver (RX) necessitates tiny gap for low bias operation and high sensitivity. In particular, the vertically stacked transducers are capable of dual frequency operation. In the second part, CMUT which is designed and fabricated using such a platform will be introduced with its performance characterization and evaluation through a series of static and dynamic measurements. In addition, an ultrasonic pulse-echo testing (Time of Flight, ToF) and directivity verification of the proposed CMUT array on CMOS will be experimentally explored in both liquid and solid media. A special emphasis on CMUT vertically integrated with its readout IC to minimize parasitics and optimize form factor will also be demonstrated.

Dr. Sheng-Shian Li received the B.S. and M.S. degrees in mechanical engineering from National Taiwan University, Taipei, Taiwan, in 1996 and 1998, respectively, and the M.S. and Ph.D. degrees from the University of Michigan, Ann Arbor, MI, USA, in 2004 and 2007, respectively, both in electrical engineering and computer science. In 2007, he joined RF Micro Devices, Greensboro, NC, USA, where he was a Research and Development Senior Design Engineer for the development of MEMS resonators and filters. In 2008, he joined the Institute of NanoEngineering and MicroSystems (iNEMS), National Tsing Hua University (NTHU), Hsinchu, Taiwan, where he is currently a NTHU Chair Professor. His research interests include microelectromechanical systems, integrated resonators and sensors, RF MEMS, CMOS-MEMS technology, front-end communication architectures, and integrated circuit design and technology. He served as the TPC/ETPC/ISC for the IEEE IFCS, IEEE Sensors Conference, Transducers Conference, IEEE MEMS Conference, and IEEE IEDM. He also serves as Associate Editors for IEEE JMEMS, IEEE Sensors Letters, IEEE Sensors Journal, and IEEE J-EDS. He was the General Co-Chair for 2025 IEEE MEMS Conference.

Non-invasive sweat glucose monitoring has emerged as a promising alternative to conventional blood glucose testing for continuous and patient-friendly health assessment. However, the clinical application of sweat-based glucose sensing remains challenging due to the complex relationship between sweat and blood glucose levels and the limited availability of clinical validation studies. In this presentation, we introduce a wearable sweat glucose biosensing platform combined with a personalized calibration strategy for estimating blood glucose levels without blood sampling. The system utilizes a simple and comfortable sweat collection approach and electrochemical sensing technology to quantify sweat glucose in real time. To establish individualized sweat-to-blood glucose relationships, personalized models were developed using paired sweat and blood glucose measurements. Clinical validation was conducted in eight hospitalized stroke patients, demonstrating that sweat glucose signals can be translated into clinically meaningful blood glucose estimates with high agreement to reference measurements. The study highlights the feasibility of sweat-based glucose monitoring in real-world clinical settings and demonstrates the potential of wearable sweat sensing technologies to support non-invasive glucose assessment, personalized healthcare, and future digital health applications.

Bor-Ran Li is a Professor and Associate Director of the Institute of Intelligent Biomedical Engineering at National Yang Ming Chiao Tung University. His research focuses on microfluidics, biosensors, wearable healthcare devices, and intelligent biomedical systems, with applications in cancer diagnostics, reproductive medicine, and personalized healthcare. He has led the development of innovative lab-on-a-chip and point-of-care diagnostic technologies, integrating microfluidic engineering, sensor platforms, and artificial intelligence for biomedical analysis. Through extensive collaborations with academic institutions, hospitals, and industry partners, Prof. Li is dedicated to translating advanced biomedical technologies into practical healthcare solutions and advancing the field of intelligent medicine.

Two-dimensional (2D) transition metal dichalcogenides (TMD) have emerged as promising semiconductors for next-generation optoelectronics, quantum information technologies, and integrated circuits due to their tunable electronic structure and rich materials chemistry. Among various synthesis techniques, metalorganic chemical vapor deposition (MOCVD) offers a scalable and industry-compatible route for the controlled growth of high-quality 2D TMD with precise control over precursor delivery. In this work, we present our recent results in the MOCVD of TMD on single-crystalline substrate at high and low temperatures. To elucidate the underlying growth mechanisms, we integrate multiscale modeling approaches, including molecular dynamics (MD), density functional theory (DFT), and kinetic Monte Carlo (KMC) to investigate domain coalescence, substrate-dependent growth kinetics, and homoepitaxial nucleation processes. Multilayer epitaxial TMD grown by MOCVD is systematically characterized using various surface techniques and evaluated in field-effect transistors at the channel length of 100 nm. These results provide critical insights into synthesis-structure-property relationships and establish practical pathways toward realization of practical 2D semiconductors on the wafer scale. We further explore the controlled incorporation of foreign elements to tailor the physical properties of TMDCs, such as Re and V into MoS₂. We employ a low-energy ion implantation strategy to engineer Janus TMDC structures, enabling the transformation of WS₂ into WSSe and WSe₂, respectively, with controlled compositional asymmetry.

Dr. Yu-Chuan Lin is an Assistant Professor in Materials Science and Engineering at National Yang Ming Chiao Tung University (NYCU), Taiwan. His research focuses on the growth, characterization, and device integration of two-dimensional (2D) semiconductors, with an emphasis on manufacturable vapor-phase synthesis techniques such as MOCVD.

He received his Ph.D. from The Pennsylvania State University in 2017 and subsequently conducted research at Oak Ridge National Laboratory and PSU. His work has led to pioneering advances in van der Waals epitaxy, Janus 2D semiconductors, and wafer-scale growth of transition metal dichalcogenides.

GaN-based micro-light-emitting diodes (µLEDs) are attractive for high-resolution displays, optical interconnects, and emerging sensing applications, but their performance is strongly limited by plasma-induced sidewall damage. As device dimensions shrink, the increased surface-to-volume ratio enhances nonradiative recombination, leakage current, and efficiency degradation, making effective sidewall treatment essential. This work investigates wet-chemical sidewall treatment methods for nanoscale GaN structures. Nanorod test structures are used to evaluate the etching behavior, surface morphology evolution, and potential removal of damaged sidewall regions. The impact of treatment conditions on optical properties is examined using cathodoluminescence (CL) and photoluminescence (PL) measurements, enabling spatially resolved assessment of defect-related emission and radiative efficiency recovery. By correlating etch performance with CL and PL signatures, this study provides insight into sidewall damage mitigation mechanisms and establishes process guidelines for improving the performance of sub-5 µm GaN µLEDs.

Dr. Matthew Wong is an Assistant Professor in the Department of Materials Science and Engineering at the University of Texas at Dallas. His research focuses on wide-bandgap semiconductor materials and devices, with emphasis on GaN-based microLEDs, laser diodes, and optoelectronic characterization. He received his Ph.D. from the University of California, Santa Barbara, where he worked on III-nitride optoelectronic devices.

The rapid growth of data traffic in high‑performance computing and cloud infrastructures has driven the demand for energy‑efficient, high‑bandwidth optical interconnects. Co‑packaged optics (CPO) has emerged as a promising solution, enabling tight integration of photonic and electronic components to overcome the limitations of traditional pluggable modules. However, conventional photonic fabrication processes often require high thermal budgets, which are incompatible with advanced packaging platforms and temperature‑sensitive substrates. This talk explores low‑temperature photonic integration on various interposers that support scalable CPO deployment. By leveraging deposition and processing techniques below 200 °C, compact and low‑loss photonic devices can be realized without compromising backend compatibility. Furthermore, heterogeneous integration approaches are discussed to enable hybrid material platforms for extended functionality. The proposed low‑temperature photonic processes highlight the potential of low‑temperature photonics as a critical enabler for next‑generation optical interconnects, offering a scalable route toward high‑performance, thermally compatible CPO systems.

Pei-Hsun Wang is an associate professor in the Institute of Electronics at National Yang Ming Chiao Tung University (NYCU), Taiwan. He received the Ph.D. degree from the School of Electrical and Computer Engineering, Purdue University, USA, in 2016. During 2016-2019, he joined Taiwan Semiconductor Manufacturing Company (TSMC) as a principal engineer in R&D pathfinding, after which he joined Department of Optics and Photonics at National Central University in 2019 as an assistant professor and later International College of Semiconductor Technology at NYCU as an associate professor. His research interests currently include co-packaged optics, nano-photonics, semiconductor fabrication, silicon photonics, FMCW LiDAR, ultrafast and nonlinear photonics, and fiber communications. He has authored and co-authored over 36 journal papers, 60 conference papers, and 22 US patents in these emerging areas. He is a Senior Member of IEEE, and a Member of SPIE and Optica (formerly OSA) and received the Ta‑You Wu Memorial Award from Taiwan’s National Science and Technology Council (NSTC) in 2026.

Miniaturized three-dimensional (3D) vision systems are becoming increasingly important for emerging applications in consumer electronics, machine vision, and wearable devices. However, conventional structured-light projectors based on vertical-cavity surface-emitting laser (VCSEL) arrays, diffractive optical elements (DOEs), and multiple optical components face fundamental challenges in size, optical alignment, and system integration. This talk presents our recent progress in integrated metasurface–photonic crystal surface-emitting laser (PCSEL) photonic devices for compact structured-light 3D vision.

First, a metasurface-based structured-light projector combined with a high-power PCSEL is demonstrated for monocular depth perception and facial recognition, achieving a wide field of view and dense infrared dot projection within a simplified optical architecture. Building upon this platform, we further demonstrate the first monolithic integration of a metasurface hologram directly on a PCSEL, realizing a chip-scale structured-light projector with a 2450-fold reduction in volume and 28.7% lower power consumption compared with commercial VCSEL–DOE modules. These results highlight the potential of metasurface-enabled photonic integration for compact, high-performance 3D vision systems and provide a promising pathway toward next-generation integrated optical devices for sensing and imaging.

Dr. Yao-Wei Huang is a Yushan Young Fellow and Associate Professor in the Department of Photonics at National Yang Ming Chiao Tung University (NYCU). He is also a Fellow of the Higher Education Academy (HEA) and a Senior Member of SPIE, the International Society for Optics and Photonics. His research focuses on nanophotonics, metasurfaces, meta-optics, inverse design, and computational imaging, with applications in integrated photonic devices, depth sensing, and extended reality. Dr. Huang has authored more than 50 journal publications in leading venues, including Nature Photonics, Nature Communications, Proceedings of the IEEE, and Nano Letters. His research has been recognized with the 2024 NSTC Future Tech Award, a 2024 Google Research Grant, and inclusion among the World's Top 2% Scientists from 2022 to 2025.

Metastable Ga2O3 polymorphs, particularly alpha- and epsilon-Ga2O3, provide unique opportunities for materials and device engineering. This talk presents our recent progress in Mist-CVD-grown (AlGa)2O3/Ga2O3 heterostructures and MOS-HFETs. Pure-phase alpha-(AlGa)2O3/alpha-Ga2O3 MOS-HFETs are first introduced to demonstrate bandgap engineering within a phase-matched heterostructure. This device concept is then extended to epsilon-(AlGa)2O3/alpha-Ga2O3 MOS-HFETs, combining metastable hetero-phase and bandgap engineering to improve channel transport while maintaining kilovolt-class breakdown characteristics. Based on this heterostructure platform, modulation doping is further explored to tailor carrier transfer and spatial distribution within the channel. In addition to high-voltage operation, the epsilon-(AlGa)2O3/alpha-Ga2O3 MOS-HFET platform is extended to an electrically driven synaptic transistor incorporating a dual quasi-delta-doping. The dual quasi-delta-doping structure is designed to exploit pulse-induced transient charge transfer, thereby enabling spike-dependent modulation of the channel conductance. These results highlight the potential of metastable Ga2O3 heterostructures as a versatile platform for high-voltage electronics and emerging neuromorphic devices.

Dr. Han-Yin Liu is an Associate Professor in the Department of Electrical Engineering at National Sun Yat-sen University, Taiwan. His research interests include Mist-CVD-grown oxide semiconductors, Ga2O3 materials and heterostructures, high-voltage transistors, and oxide-based synaptic transistors. He has received the Outstanding Young Scholar Award from the Electronic Devices and Materials Association (EDMA), the Outstanding Young Electrical Engineer Award from the Chinese Institute of Electrical Engineering (CIEE), the Pride of the Nation Academic Award for Outstanding International Achievement presented by the International Inventor Prize (IIP), and the Best Young Professional Member Award from the IEEE Tainan Section.

This presentation introduces a novel dual-cell inferring True Random Number Generator (TRNG) based on a 4.3-bit/cell multi-resistance-state 1T1R RRAM macro fabricated in a 40-nm CMOS process. By leveraging a gradual-FORMing and incremental SET/RESET modulation scheme, 20 distinct resistance states are established to achieve fine-grained entropy extraction. The proposed architecture utilizes a dual-cell interference mechanism integrated with an Offset-Canceling Current-Sampling Sense Amplifier (OCCS-SA) to harvest nanoscale stochasticity from resistance crossover events.

Crucially, this mechanism establishes a mathematical isomorphism between hardware stochasticity and biological DNA mutations, drastically accelerating hardware-mapped Genetic Algorithms by reducing operational complexity from O(N) to O(M). Experimental results confirm that the generated bitstreams pass all NIST SP 800-22 tests with an exceptional energy efficiency of 1.095 pJ/bit and high-temperature robustness up to 150°C, paving the way for low-power bio-inspired stochastic computing within compute-in-memory frameworks.

Associate Professor E-Ray Hsieh, now at NYCU's Institute of Electronics, is a prominent researcher in Memory Devces and Memory circuit. His expertise in next-generation non-volatile memory was shaped as a visiting scholar at Stanford University (2018–2019).

At National Central University (2020–2024), he established a research group dedicated to neuromorphic computing and in-memory processing, earning recognition in top journals and conferences while securing competitive funding and industry collaborations.

Moving to NYCU in 2024, Professor Hsieh continues to advance memory applications, cementing his role as an emerging leader in microelectronics.

This talk explores the ongoing development of highly scalable quantum systems founded on silicon spin qubits, which are fabricated utilizing standard CMOS technology. This work highlights the critical importance of industrial and academic effort, showcasing robust collaborative research efforts among National Tsing Hua University (NTHU), the Taiwan Semiconductor Research Institute (TSRI), AMD, and TSMC. Together, we systematically investigate quantum dot fabrication processes by leveraging isotopically enriched ²⁸Si in conjunction with wafer-scale Silicon-On-Insulator (SOI) technology. To optimize device performance, we examine fabrication variables, specifically focusing on the precise effects of arsenic-based ion implantation profiles and metal gate exploration. Furthermore, we adopt a novel cryogenic method that is designed to provide high-fidelity characterization. By comparing both room temperature and sub-Kelvin condition test results, we can compare standard transistor behavior with the unique properties of the engineered quantum dots. Finally, we correlate these experimental results with advanced theoretical QTCAD simulations. This comparative analysis of the physical processes governing few-electron quantum dot formation actively explores the potential for the milli-Kelvin operation of ²⁸Si electron spin qubits manufactured entirely within an industry-standard research foundry process.

Chien-Yuan (Ted) Chang is an Assistant Professor at National Tsing Hua University (NTHU). With a Ph.D. from Georgia Tech and prior research experience at RIKEN and the University of Tokyo, he specializes in solid-state quantum computing. He is currently developing silicon-based semiconductor qubits and building a full-stack quantum system at NTHU.