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The rapidly rising energy demand of computing is shifting the central challenge of transistor scaling from device density alone to energy per operation. Atomically thin semiconductors such as MoS₂ and WSe₂ offer strong electrostatic control and favorable carrier transport at aggressively scaled dimensions, providing a promising pathway toward high-performance electronics operating at substantially reduced power. Realizing these advantages in practical devices, however, requires not only scalable growth of electronics-grade 2D semiconductors, but also precise engineering of the interfaces that govern transistor operation. Of particular importance are the metal–2D interfaces, where Fermi-level pinning, carrier injection, contact resistance, and contact-length scaling critically determine device performance, and the high-κ dielectric–2D interfaces, where dielectric integration, interface quality, and threshold-voltage control determine gate efficiency, leakage, and low-voltage operation. This will review recent progresses in addressing these issues and the integration into complementary MoS₂/WSe₂ transistors and CFET circuits. Together, these advances illustrate a pathway for translating the intrinsic scaling advantages of 2D semiconductors into practical ultra-low-power electronics beyond silicon.

Dr Lain-Jong (Lance) Li is currently a Distinguished Professor in the Department of Materials Science at the National University of Singapore, as well as the NRF Professor awarded by NRF Singapore. He has held prominent positions such as Chair Professor of Future Electronics in the Department of Mechanical Engineering at The University of Hong Kong, as well as Director of the Corporate Research at Taiwan Semiconductor Manufacturing Company (TSMC 2017-2020). He is a Fellow of the Royal Society of Chemistry and serves as an Associate Editor of Nano Letters for the American Chemical Society. He has collected >100,000 citations and h-index 145. He has been also the highly cited scholar (2018-now). His research is focusing on advanced device technologies for ultra-scaled and energy-efficient transistors based on emerging semiconductor materials.

This talk presents an overview of embedded single and two-phase chip cooling technology designed for high-performance electronics. By synergizing 3D manifold distribution layers with capillary micropillar arrays, our unified microfluidic architecture enables highly efficient, regulated two-phase flow boiling using eco-friendly water. This advanced thermal management solution achieves a record-high coefficient of performance up to 105 and a critical heat flux of 770 W/cm² with minimal pumping power. Our strategy paves the way for sustainable, high-power-density cooling in next-generation artificial intelligence chips and power semiconductor devices.

Masahiro Nomura is a professor at the Institute of Industrial Science, the University of Tokyo. He received his Ph.D. degree in Applied Physics from the University of Tokyo in 2005. He is a Special Advisor to the President and the Director of LIMMS/CNRS-IIS, The University of Tokyo. His current research interests include semiconductor device thermal management, physics and control technology of phonon/heat transport in semiconductor nanostructures, radiative heat transfer, thermoelectric energy harvesting, and hybrid quantum science. The concept of his current research is "from photonics to phononics" using phononic crystals, which have some physical analogies to photonic crystals. Since 2017, he has been the chairman of the Phonon Engineering Group of the Japan Society of Applied Physics. He has received 20 awards, including the Nukiyama Memorial Award (2026), the MEXT Science and Technology Award (2026), the 23rd Docomo Mobile Science Award, the 16th JSPS Prize (2019), the German Innovation Award Gottfried Wagener Prize (2019), the Young Scientist Award in Science and Technology, MEXT Japan (2012).

AI workloads are transforming traditional computing. As models grow and real-time inference proliferates, they place unprecedented demands on memory latency, bandwidth, and density. Historically, embedded memories have offered high bandwidth and low latency, and for the last half-century SRAM has served as the primary embedded memory technology. This talk will trace SRAM scaling from early technology nodes to today’s advanced processes, illustrating how dimensional scaling for density increase has, by necessity, evolved into a paradigm of Design-Technology Co-Optimization (DTCO). It will then examine how advances in heterogeneous integration and advanced packaging have introduced a new dimension to scaling, challenging the traditional boundary between embedded and discrete memories. Finally, the talk will look ahead to the future, exploring how emerging materials and technologies can further propel AI performance and energy efficiency, redefining the role of embedded memories within an increasingly data-centric computing landscape.

John Wuu is a Senior Fellow Design Engineer at AMD in Fort Collins, Colorado, specializing in memory technology and design, high performance cache design, and chiplet DTCO. In addition to working across the company to define and deliver memory solutions, his recent contributions included the physical definition and technology co-development for AMD’s 3D V-Cache™. Prior to joining AMD in 2006, he had been with Hewlett-Packard and then Intel, working on large L3 caches for Itanium processors. He received his bachelor’s and master’s degrees from MIT in 1997, and currently serves as the Memory Subcommittee Chair for ISSCC, and Symposium Co-Chair for the VLSI Symposium.

In commemoration of the 100th anniversary of the field-effect transistor (FET), this talk focuses on thin-film transistors (TFTs), a class of FETs which has been widely investigated by virtue of its importance in modern electronic systems. This presentation reviews the evolution of TFT technologies since the conceptual proposal of the FET by Julius Edgar Lilienfeld in 1925. A defining feature of TFTs is that all functional layers are fabricated as thin films using deposition-based techniques, typically at relatively low processing temperatures. This approach enables flexible control of layer sequencing and stacking, allowing the realization of diverse device structures and architectures. The electrical performance of TFTs is strongly influenced by the choice of thin-film materials and the fabrication conditions. The fundamental operating principles are outlined, with emphasis on charge transport and field-effect modulation in thin-film semiconductor channels. The complex interdependence between material properties, processing methods, and transistor characteristics is also examined. Representative applications in emerging electronics, photonics, and sensing technologies are highlighted to demonstrate the versatility of TFT systems. Finally, recent advances in TFT research and the key challenges for next-generation applications are discussed.

Arokia Nathan is a pioneer in thin-film transistor technologies, contributing to flexible electronics, advanced displays, sensors, and millimetre-wave radios on glass. He earned his PhD from the University of Alberta (1988) and worked at LSI Logic and ETH Zürich before joining the University of Waterloo. In 2006, he became Sumitomo Chair of Nanotechnology at University College London, and in 2011 moved to the University of Cambridge as Chair of Photonic Systems and Displays, where he is currently a Bye Fellow and Graduate Tutor at Darwin College. He also holds a Distinguished Professorial Chair at School of Information Sciences, Shandong University, Qingdao, China. He has authored 600+ publications, holds 150+ patents, founded four companies, and received numerous prestigious fellowships and the 2020 IEEE J. J. Ebers Award.